figure 1.  cooling power density for different t.e. cooler designs 
(adaped from vandersande and fleurial [6]).

introduction

many advances in computer technology have been made possible by increases in the packaging density of electronics. these advances began with the introduction of the transistor in 1947 and continue today with ultra-large scale integration at the chip level coupled with multi-chip modules. the combination of increased power dissipation and increased packaging density led to substantial increases in chip and module heat flux over the past 40 years, particularly in high-end computers.

during this time the challenge was to limit chip temperature rise above the ambient coolant temperature to ensure satisfactory circuit operation and reliability.

throughout this period virtually all commercial computers were designed to operate at temperatures above ambient, generally in the range of 60° to 100°c. however, the potential for low temperature enhancement of cmos electrical performance has been recognized for some time, going back as far as the late 1960's. researchers identified the advantages of operating electronics at low temperatures. these advantages include: faster semiconductor device switching; increased speed due to lower electrical resistance of interconnecting materials; and a reduction in thermally induced failures.

until recently the only computer to take advantage of the operation of cmos chips at low temperature was the eta-10 [1], a large-scale scientific computer.  this machine utilized direct immersion cooling of single chip modules immersed in liquid nitrogen. in 1997 ibm announced and shipped the ry5 s/390 mainframe, which uses a conventional refrigeration system to maintain chip temperatures below that of comparable air-cooled systems, but well above cryogenic temperatures. since then there have been indications that other manufacturers may be developing refrigeration cooled computers.

in addition, the scaling limits of cmos devices -- and how to achieve performance gains as scaling limits are approached -- has received increased attention in the semiconductor electronics community. operation at lower temperature is seen as a means to further extend cmos performance. these developments not only foreshadow further applications of refrigeration cooling of electronics, but also potential opportunities to apply thermoelectric cooling to computer electronic packages.

thermoelectric cooling

although the principle of thermoelectricity dates back to the discovery of the peltier effect in 1834 [2], there was little practical application of the phenomenon until the middle 1950s. prior to then, the poor thermoelectric properties of known materials made them unsuitable for use in a practical refrigerating device.

as discussed by nolas et al. [3], from the mid-1950s to the present the major thermoelectric material design approach was that introduced by a.v. ioffe, leading to semiconducting compounds such as bi₂te₃ , which is currently used in thermoelectric coolers. these materials made possible the development of practical thermoelectric devices for attaining temperatures below ambient without the use of vapor-compression refrigeration.

thermoelectric coolers offer the potential to enhance the cooling of electronic module packages to reduce chip operating temperatures or to allow higher module powers. thermoelectric coolers also offer the advantages of being compact, quiet, free of moving parts, and their degree of cooling may be controlled by the current supplied.  unfortunately, compared to vapor-compression refrigeration, they are limited in the heat flux that they can accommodate and exhibit a lower coefficient of performance (cop). these two limitations have generally limited thermoelectrics to niche applications characterized by relatively low heat flux.

in recent years there has been increased interest in the application of thermoelectrics to electronic cooling, accompanied by efforts to improve  their  performance through the development of new bulk materials and thin film microcoolers. the usefulness of thermoelectric materials for refrigeration is often characterized by the dimensionless product, zt, of the thermoelectric figure of merit z and temperature t (in k). the value of the thermoelectric figure of merit is given by

where α is the seebeck coefficient, ρ is the electrical resistivity, and k is the thermal conductivity.

fleurial et al. [4] reported that in 1991 jpl started a broad search to identify and develop advanced thermoelectric materials. among the materials considered, skutterudite and zn₄sb₃ -based materials appeared particularly promising and several of these materials are being developed. zt values equal to or greater than 1 have been obtained for these materials over different ranges of temperature varying from 375° to 975° k.

however, to be particularly useful for electronic cooling applications, improvements in zt are needed over the temperature range of 300° to 325° k or below.  another strategy for enhancing zt being pursued by researchers at mit, harvard, and ucla focuses on reduced dimensionality as occurs in quantum wells (2d) or quantum wires (1d) [5].

a number of recent papers discussed the potential advantages of thin film thermoelectric coolers. vandersande and fleurial [6] proposed to mount high power components on a diamond substrate, which would be the top or cold side substrate of a thin film thermoelectric cooler. they noted that "the main benefit of going to thin film coolers is the dramatic increase in cooling power density since it is inversely proportional to the length of the thermoelectric legs." as shown in figure 1, they reported the possibility of achieving cooling power densities above 100 w/cm². the structure of such a thin film thermoelectric element is shown in figure 2.

figure 2.  structure for a thin film thermoelectric device
(adapted from fleurial and vandersande [6]).

the heat pumping capacity, qp , of a thermoelectric cooling module is given by:

where n is the number of couples, g is the ratio of cross-sectional area/length of each thermoelectric element, i is the electrical current, and t_c is the cold side temperature in k, and dt is the temperature difference (t_h-t_c)  between the hot side and cold side of the thermoelectric elements. the heat, q_te, dissipated by a thermoelectric cooling module to perform the electronic pumping action is given by

and the coefficient of performance, cop, is given by"

these equations will be used to determine allowable module heat load or chip temperature with thermoelectric enhancement in an example of an mcm cooling application.

mcm thermoelectric cooling application

for the example application, a 126 mm x 126 mm  (4.96" x 4.96") mcm containing thirty 15 mm x 15 mm (0.59" x 0.59") chips was assumed.

figure 3.  simplified cross-sectional view of a central processor module level package with thermal grease conduciton paths.

a layer of enhanced thermal grease was assumed between the chip and hat as shown in figure 3. in considering the use of thermoelectric modules to enhance cooling, it is necessary to compare cooling performance with and without thermoelectrics. figure 4 illustrates the cross-section of a chip site on the mcm with and without a thermoelectric module. heat flows via a serial path from chip to coolant through the thermal resistances called out in figure 4.

figure 4.  cross-section view of chip site on mcm showing thermal resistances
w/ and w/o thermoelectric module augmentation.

the thermoelectric heat pumping equation (2) and heat dissipation equation (3) may be used to determine either allowable module power dissipation, q_m, for a specified chip temperature, t _chip, or chip temperature for a specified module power. two additional equations relating chip temperature to cold-side temperature (t_c) and hot-side temperature (t_hot) to the coolant temperature (t_o) are required.

the chip temperature is related to the thermoelectric cold-side temperature by:

where r₀ is the sum of thermal resistances across the chip, grease layer, and thickness of  the hat, and r₁ is the thermal resistance across the interface between the hat and heat sink  base or between the hat and the cold-side of the thermoelectric module. the thermoelectric hot-side temperature is related to the coolant temperature, t_o, by

where r₂ is the thermal resistance across the interface between the hot-side of the thermoelectric module and the base of the heat sink, and r₃ is the thermal resistance from the heat sink base to the cooling fluid.

for steady-state operation, heat pumping capacity, q_p, given in equation (2) will be equal to the module power dissipation term, q_m, in equations (5) and (6). equations (2), (3), (5), and (6) were combined to obtain equations (7) and (8) shown in table 1. (see overleaf) given the material and thermoelectric module parameters, electrical current supplied to the thermoelectric module, and thermal resistances; chip temperature may be determined for a given module power using equation (7).

the allowable module power may be determined for a given chip temperature using equation (8). these equations may also be applied to single chip modules by setting module power dissipation equal to chip power dissipation.

for multi-chip modules, application of these equations is restricted to uniform power dissipation on all chips. it should be noted that all of the thermal resistances contained in equations (5), (6), (7), and (8) should be computed on an overall module basis. accordingly, thermal resistance, r₀, should be computed for an individual chip site and then divided by the number of chips on the mcm to convert it to an overall module basis before using it in any of the equations.

table 1.  chip temperature and allowable power dissipation equations
for thermoelectric module augmentation.

a commercially available 62 mm x 62 mm (2.44" x 2.44") thermoelectric module was chosen for use in the example presented here. the module chosen was picked because of its size, which would allow four modules to nearly cover the surface of the mcm. the thermoelectric module parameters used in the calculations were:

α = 0.0002 volts/k                                 n = 127
ρ = 0.001 ohm-cm                                   g = 0.28 cm.
k = 0.015 watt/cm-k                              i  = 14 amps

since each thermoelectric module covered one-quarter of the mcm, the thermal resistances and module power were scaled accordingly. the thermal resistance values and coolant reference temperatures used in the calculations were:

r₀   =  0.034                          k/w
r₁   =  0.0054                         "
r₂   =  0.0054                         "
r₃   =  0.116                           "             (air-cooled)
r₃   =  0.0168                         "             (h ₂o-cooled)
t_o   =  30  °c                          "             (air-cooled)
t_o   =  25  °c                          "             (h ₂o-cooled)

the values of interface thermal resistances (r₁ and r₂ ) used were based upon the interface thermal resistance achieved with the ibm es/9000 tcm cooling technology [7]. similarly the values used for heat sink (air) and cold plate (h₂o-cooled) thermal resistance (r3) were based upon ibm high performance cooling technology scaled for one-quarter of the size of the mcm.

the equations presented in table 1 were incorporated in a lotus 1-2-3 spreadsheet and executed with the above values. comparable equations for the case without thermoelectric augmentation were also included in the spreadsheet. the equation giving chip temperature for a specified module power is

and the equation giving allowable module power for a specified chip temperature is

an example of the t.e. spreadsheet calculator screen is shown in figure 5. as noted earlier, thermoelectric cooling modules may be used to reduce chip operating temperatures given a module heat load. the magnitude of temperature reduction for a given design is found by subtracting the results of equation (7) from the results of equation (9). chip operating temperature reductions, which could be achieved by applying thermoelectric cooling enhancement to the example mcm, are shown in figure 6.

figure 5.  lotus 1-2-3 t.e. spreadsheet calculator screen.

 
figure 6.  module temperature reduction versus module power for air or
water-cooled 126 mm x 126 mm multi-chip modules.

considering the cost of the thermoelectrics, the added manufacturing process steps, the additional power requirement, and the added reliability risk associated with the thermoelectrics, it is doubtful that they would be considered for anything less than a 20°c reduction. it may be seen that for the example mcm a 20°c temperature reduction would occur at an mcm power of 275 watts for the air-cooled case and at 335 watts for the water-cooled case.

it was also noted earlier that thermoelectric cooling modules may be used to enhance allowable module power dissipation at a given temperature. comparisons of allowable module power dissipation with and without thermoelectric enhancement are shown in figure 7 (see overleaf). for the air-cooled case, at a chip temperature of 47°c, the allowable module power dissipation is the same with or without enhancement.

figure 7.  comparison of allowable module heat load with and
without thermoelectric cooling enhancement.

at higher chip temperatures the allowable module power dissipation is greater without thermoelectric augmentation. a similar situation occurs for the water-cooled case at a chip temperature of 31°c. in both cases the power dissipation at which this occurs at is about 450 to 500 watts. clearly, the application of thermoelectrics must be carefully assessed to determine if the use of thermoelectrics will be beneficial.

conclusion

a new dimension has been added to the cooling challenge by the requirement to reduce operating temperatures to achieve enhanced speed. with the continued demand for improved cooling technology to enhance the performance and reliability of cmos applications, thermoelectric cooling may be considered a potential candidate for cooling enhancement.

the chip temperature (7) and allowable module power (8) equations presented here provide a useful means to perform trade-off analyses to assess whether or not thermoelectric augmentation will be advantageous over conventional cooling techniques. to use these equations, detailed information in terms of the parameters , , k, and g pertaining to the thermoelectric module under consideration is required. unfortunately, today only one thermoelectric vendor provides such information in their data sheets. it is to be hoped that in the future other thermoelectric vendors will also make such information available for users.

as shown in the example, the application of thermoelectric coolers could provide cooling enhancement for a limited range of powers. unfortunately, in many cases mcm powers may be simply too high for current thermoelectric modules to handle effectively. the current figure of merit, z, of the available candidate materials, and the coefficient of performance (cop) attainable with existing thermoelectric coolers, need to be increased

until and unless improvements can be made to enhance heat pumping capability and cop, thermoelectrics will not be a serious candidate for higher power electronic cooling applications. it is hoped that the work being done on development of improved thermoelectric materials and thin film thermoelectrics will eventually alter this situation.

robert e. simons
ibm
(senior staff member - retired)

references
1. krane, r.j., bar-cohen, a., jaeger, r.c., and gaensslen, f.h., "mos electronics and thermal control for cryogenically-cooled computer systems," in advances in thermal modeling of electronic components and systems, vol. 2, asme press, new york, ny, pp. 185-232, 1990.

2.godfrey, s., "an introduction to thermoelectric coolers," electronics cooling, vol. 2, no. 3, pp. 30-33, 1996.

3. nolas, g.s., slack, g.a., cohn, j.l., and schujman, s.b., "the next generation of thermoelectric materials," proceedings of the 17th international conference on thermoelectrics," pp. 294-297, 1998.

4. fleurial, j-p., borshchevsky, a., caillat, t., and ewell, r., "new materials and devices for thermoelectric applications," iecec, acs paper no. 97419, pp. 1080-1085, 1997.

5. dresselhaus, m.s., koga, t., sun, x., cronin, s.b., wang,  cronin, s.b., wang, k.l., and chen, g., "low dimensional thermoelectrics," proceedings of the 16th international conference on  thermoelectrics, pp. 12-20, 1997.

6. vandersande, j.w., and fleurial, j-p., "thermal management of power electronics using thermoelectric coolers," proceedings of the 15th international conference on thermoelectrics, pp. 252-255, 1996.

7. chu, r.c., and simons, r.e., "cooling technology  for high performance computers: design applications," in cooling of electronic systems, edited by kakac, s., yuncu, h., and hijikata, k., kluwer academic publishers, dordrecht, netherlands, pp. 71-95, 1994.